# Chipset, PCIe lanes and USB controllers: interfaces are not bandwidth

> Why a board with four M.2 slots may only run two at full speed, how lane sharing shows up in Windows, and what to check in the manual before buying.

**Tested on**

- Build: 26300.9457
- Edition: Pro (26H2)
- Architecture: x64
- Evidence: E1
- Verified: 2026-10-29

## The short answer

A motherboard's port count is marketing; its **lane budget** is engineering. Two numbers decide what you can actually run at once:

- **CPU lanes** — usually 16 for the GPU, 4 for the first M.2, and 4 for the chipset link.
- **Chipset lanes** — shared among the remaining M.2 slots, SATA ports, USB controllers, extra PCIe slots and the network chip.

Populate the wrong combination and the board **splits** lanes (x16 → x8/x8) or **disables** a SATA port. Nothing warns you in Windows; a drive is simply slower or missing.

## The usual lane map

| Device | Usually connected to | Notes |
|---|---|---|
| GPU slot | CPU, 16 lanes | splits to x8/x8 if a second slot is used |
| First M.2 | CPU, 4 lanes | always full speed |
| Second/third M.2 | chipset | shares with SATA/USB |
| SATA ports | chipset | a populated M.2 may disable two |
| 2.5GbE / Wi-Fi | chipset | one lane |
| USB 3.x controllers | chipset | each controller needs lanes |
| Thunderbolt/USB4 | CPU or chipset | often costs 4 lanes |

This is why a board can advertise "4× M.2, 6× SATA" and still ship with a manual page that says **M2_3 shares bandwidth with SATA_5/6**.

## Check before you buy

1. Open the board's **block diagram** or "lane sharing" table in the manual (not the marketing page).
2. Count what you will actually populate: GPU + how many NVMe + how many SATA.
3. If the answer needs more than the CPU provides, the chipset is carrying it — and everything on the chipset shares one uplink (usually PCIe 4.0 ×4).

Two rules that avoid most disappointment:

- Put the **fastest NVMe in the CPU-connected slot** (usually M2_1).
- Do not expect **two NVMe drives + a SATA array + 10GbE** to run at full speed on a mainstream chipset.

## What Windows can and cannot tell you

```powershell
Get-PnpDevice -Class Display | Select-Object FriendlyName,Status
Get-Disk | Select-Object Number,FriendlyName,BusType,Size
Get-PnpDevice -Class SCSIAdapter | Select-Object FriendlyName,Status
Get-NetAdapter | Select-Object Name,LinkSpeed,DriverVersion
```

- `BusType` shows `NVMe`/`SATA`/`RAID`, not the link width.
- Device Manager **View → Devices by connection** shows which root port a device hangs from — the closest thing to a lane map Windows offers.
- Link width and generation are firmware/PCIe config space facts; the OS does not surface them in a supported UI. Vendor tools (GPU-Z, HWiNFO) read them.

If a GPU reports x8 instead of x16 on a board with one GPU installed, check whether an M.2 slot is stealing lanes.

## USB is not one big pipe either

USB ports are grouped behind **controllers**, and controllers share the chipset uplink.

- A 10Gbps SSD and a capture card on the same controller will contend.
- Front-panel and rear-panel ports are often on different controllers — moving a device can fix intermittent dropouts.
- Hubs add a shared bottleneck, not bandwidth.

```powershell
Get-PnpDevice -Class USB | Where-Object Status -eq 'OK' | Select-Object FriendlyName,InstanceId
```

`InstanceId` prefixes group devices by controller/hub path.

> **Caution: A second GPU is a lane decision, not a slot decision**
>
> Two GPUs on a consumer board means x8/x8. For gaming that is a small loss; for compute with PCIe traffic it is a large one. If you need full x16 twice, you need a workstation/HEDT platform.

## What this changes in practice

| You want | Check |
|---|---|
| Fast NVMe + big SATA array | whether M.2 disables SATA ports |
| Two NVMe in RAID | both on CPU or chipset lanes consistently |
| 10GbE + two NVMe | chipset uplink saturation |
| eGPU or capture card | which controller the port belongs to |
| Future GPU upgrade | whether the slot is x16 electrical, not just x16 physical |

## Related

- [First boot checklist](https://windows.homes/en/hardware/build/first-boot/)
- [NVMe generations](https://windows.homes/en/hardware/storage/nvme-generations/)
- [Hardware requirements by OS version](https://windows.homes/en/hardware/buy/os-hardware-matrix/)

## Lab boundary

E1. Lane mapping is a board-design fact documented by motherboard vendors; Microsoft documents the PCI driver model, not your board's wiring. The lab has no physical motherboard to inspect.

## Sources

- [Microsoft Learn — PCI drivers](https://learn.microsoft.com/en-us/windows-hardware/drivers/pci/)
- [Microsoft Learn — Minimum hardware requirements](https://learn.microsoft.com/en-us/windows-hardware/design/minimum/minimum-hardware-requirements-overview)
- [Microsoft Learn — Windows processor requirements](https://learn.microsoft.com/en-us/windows-hardware/design/minimum/windows-processor-requirements)

---

Source: https://windows.homes/en/hardware/cpu/chipset-lanes/